系统框架层提供了很多方法，但是都没有对应的API提供给App开发者，比如挂断电话的方法API中就没有。
那么如何实现调用系统底层未提供的服务呢？
其实很简单，从Android Framework中拷贝出对应的aidl文件，在App中建立对应的文件夹路径，将Aidl文件拷贝进去，使用Service调用即可。
{"xComments":"UCEMS（Unified Communications Element Management System），即统一通信网元管理系统，采用客户端/服务器端结构，为华为IAD、IP PBX、SIP GW等多个设备提供集中管理和维护的功能，并通过北向接口接入到运营商统一网管中，UCEMS客户端可以在公网中，也可以在私网中。 华为UCEMS已经在全球60多个国家/地区的100多个运营商进行部署。 <br><br>\n\n华为UCEMS系统亮点：分权分域管理； 远程批量管理；资源信令跟踪；实时告警监控；可视化拓扑管理。","12":[{"HW_U_131342":"/ucmf/groups/entpublic/documents/enterprise_webasset/hw_u_131342.jpg"}],"URL":"http://www-beta.huawei.com/ucmf/groups/entpublic/documents/enterprise_webasset/hw_u_131333.docx","13":[{"HW_U_131341":"/ucmf/groups/entpublic/documents/enterprise_webasset/hw_u_131341.jpg"}],"39":[{}],"dDocTitle":"UCEMS","dDocName":"HW_U_131333","xHW_Keywords":"","webURL":"http://www-beta.huawei.com/cnenterpriseapp/1336/hw-u_131333.htm","dID":"179413"}
{"xComments":"SoftCo5500 IP语音交换机是华为IP Telephony的中小容量交换设备，面向300用户以内企业，提供专业的IP语音。产品集成度高，宽窄带一体化设计，支持本地模拟用户接入及远程综合接入设备IAD和IP 电话用户的接入，实现模拟电话和IP电话的混合组网。设备支持交直流电源及电源的1＋1备份配置，并支持统一网管和可视化工具快速开局。<br><br>\nSoftCo5500有效提高企业部署及通信效率，助力企业价值提升。","12":[{"HW_U_131409":"/ucmf/groups/entpublic/documents/enterprise_webasset/hw_u_131409.png"}],"URL":"http://www-beta.huawei.com/ucmf/groups/entpublic/documents/enterprise_webasset/hw_u_131386.docx","13":[{"HW_U_131410":"/ucmf/groups/entpublic/documents/enterprise_webasset/hw_u_131410.jpg"}],"39":[{}],"dDocTitle":"SoftCo5500 IP语音交换机","dDocName":"HW_U_131386","xHW_Keywords":"","webURL":"http://www-beta.huawei.com/cnenterpriseapp/1756/hw-u_131386.htm","dID":"179414"}
{"xComments":"The Huawei Integrated Access Device eSpace IAD132E(T) (IAD132) is a remote access device for IP private branch exchanges (PBXs) that delivers small-capacity voice over IP (VoIP) and fax over IP (FoIP) access services to small- and medium-sized branches of enterprises. <br/><br/>\nThe IAD132 supports local user access, power-off survivability and local switch. It provides 32 foreign exchange station (FXS) interfaces or 16 FXS interfaces plus 16 foreign exchange office (FXO) interfaces, allowing employees to seamlessly access enterprises' broadband networks where they can benefit from premium and cost-effective services. Flexible networking configurations and quality of service (QoS) policies enable the IAD132 to provide effective quality assurance for delay-sensitive voice services and packet loss-sensitive fax services, thereby offering end-users high-quality voice and fax services.","12":[{"EN_IAD132E_LIST":"/ucmf/groups/entpublic/documents/enterprise_en_webasset/en_iad132e_list.jpg"}],"URL":"http://www-beta.huawei.com/ucmf/groups/entpublic/documents/enterprise_en_webasset/en_iad132e.docx","13":[{"EN_IAD132E_BANNER":"/ucmf/groups/entpublic/documents/enterprise_en_webasset/en_iad132e_banner.jpg"}],"39":[{}],"dDocTitle":"Integrated Access Device \u2013 eSpace IAD132E(T)","dDocName":"EN_IAD132E","xHW_Keywords":"","webURL":"http://www-beta.huawei.com/enenterpriseapp/1755/en-iad132e.htm","dID":"197942"}
在bsp包初始化的过程中，系统会根据用户在user_config.h文件中的宏定义，选择性地初始化gpio。
1、文件Init_bsp.c (source\bsp\twrk60n512)中，代码：
/* Install the GPIO driver */
#if BSPCFG_ENABLE_GPIODEV
_io_gpio_install("gpio:");
#endif
/*FUNCTION*-------------------------------
*
* Function Name : _io_gpio_install
* Returned Value : _mqx_uint a task error code or MQX_OK
* Comments :
* Install a gpio driver.
*
*END*----------------------------------*/
_mqx_uint _io_gpio_install
(
/* [IN] A string that identifies the device for fopen */
/* input values are those identifiers defined in io_gpio.h file */
char_ptr identifier
)
{ /* Body */
if (IO_OK == gpio_cpu_init())
return _io_dev_install(identifier,
_io_gpio_open,
_io_gpio_close,
_io_gpio_read,
_io_gpio_write,
gpio_cpu_ioctl,
NULL);
return (_mqx_uint)IO_ERROR;
} /* Endbody */
/*FUNCTION*****************************************************************
*
* Function Name : gpio_cpu_install
* Returned Value : IO_OK
* Comments :
* Performs basic initialization specific to board
*
*END*********************************************************************/
_mqx_int gpio_cpu_init()
{ /* Body */
_bsp_gpio_io_init();
return IO_OK;
} /* Endbody */
/*FUNCTION*-------------------------------
*
* Function Name : _bsp_gpio_io_init
* Returned Value : MQX_OK or -1
* Comments :
* This function performs BSP-specific initialization related to GPIO
*
*END*----------------------------------*/
_mqx_int _bsp_gpio_io_init
(
void
)
{
/* Enable clock gating to all ports */
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK \
| SIM_SCGC5_PORTB_MASK \
| SIM_SCGC5_PORTC_MASK \
| SIM_SCGC5_PORTD_MASK \
| SIM_SCGC5_PORTE_MASK;
return MQX_OK;
}
#define SIM_SCGC5 SIM_SCGC5_REG(SIM_BASE_PTR)
#define SIM_SCGC5_REG(base) ((base)->SCGC5)
/* SIM - Peripheral instance base addresses */ /** Peripheral SIM base pointer */ #define SIM_BASE_PTR ((SIM_MemMapPtr)0x40047000u)
/** SIM - Peripheral register structure */
typedef struct SIM_MemMap {
uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
uint8_t RESERVED_0[4096];
uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
uint8_t RESERVED_1[4];
uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
uint32_t SOPT6; /**< System Options Register 6, offset: 0x1014 */
uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
uint8_t RESERVED_2[8];
uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
} volatile *SIM_MemMapPtr;
分析1：
地址0x40047000u是SIM模块在K60整个地址空间中的基地址，SIM模块占用一块连续的存储空间，作为自己的操作寄存器，为了操作方便，头文件中把这些寄存器定义成了一个空间结构体。这样，只要基地址正确，结构体中变量正好对应SIM的各个寄存器地址，当然也包括一些保留字节。
该地址定义位于文件K60P100M100SF2RM.pdf 文件的12.1 Memory map and register definition一节中。部分截图如下：
可以对照该结构体和文档地址空间定义进行分析理解。((SIM_MemMapPtr)0x40047000u)语句对物理地址进行了强制类型转换，然后根据结构体空间的顺序紧凑性，就可以得出：SIM_SCGC5_REG(SIM_BASE_PTR)语句就是操作了SCGC5寄存器，给里边的相应位置数操作。
6、文件MK60DZ10.h(source\psp\cortex)中，代码:
#define SIM_SCGC5_PORTA_MASK 0x200u #define SIM_SCGC5_PORTA_SHIFT 9 #define SIM_SCGC5_PORTB_MASK 0x400u #define SIM_SCGC5_PORTB_SHIFT 10 #define SIM_SCGC5_PORTC_MASK 0x800u #define SIM_SCGC5_PORTC_SHIFT 11 #define SIM_SCGC5_PORTD_MASK 0x1000u #define SIM_SCGC5_PORTD_SHIFT 12 #define SIM_SCGC5_PORTE_MASK 0x2000u #define SIM_SCGC5_PORTE_SHIFT 13
从文档12.2.12 System Clock Gating Control Register 5 (SIM_SCGC5) 中可以看到，这些宏定义分别对应着ABCDE端口的始终脉冲门。在这里是打开了这些端口的时钟脉冲门，进行初始化。
我大概猜测一下：这些脉冲门，主要是控制给对应模块的时钟信号供给，当关闭脉冲门，就相当于关闭信号来源，那么就关闭了对应端口，可以达到省电的目的。为什么GPIO口还需要这些呢，其实当GPIO不管是输入还是输出，都有脉冲进行控制。当输出时，这些脉冲门信号供给，决定了你输出信号的响应时间，当信号频率越高，那么响应时间越短；当输入时，也是一样的道理，在微观上，当有外部信号过来，必须等到该引脚内部有脉冲输入的时候，他才能检测到你的外部信号过来，这里边同样有响应时间的问题。除了可以选择打开关闭，是不是还要有给GPIO口设置参考频率的寄存器，暂时还没有发现，不过我估计即便这个芯片没有，别的芯片可能也会有。