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▪无锁同步栈实现 public class ConcurrentStack<E> {
private AtomicReference<Node<E>> top = new AtomicReference<Node<E>>();
ConcurrentStack(){
}
.........
▪OpenRisc-22-添加自己的DMA-like ipcore到ORSoC并测试 引言
之前写了一个wishbone接口的slave，work的很好。
但是要想实现一个功能完成的ipcore，必然要有master接口。
这次就写一个ipcore（mycore），既包含slave，又包含master。
一个具有类似DMA功能.........
▪nginx的$request_time和$upstream_response_time监控 前言
今天老师在trello上给我提了个任务，就是修改nginx的日志格式，对nginx进行监控，因此又接触了两个nginx常用参数，这里记录一下
$request_time&&$upstream_response_time
首先，解释一下.........
[1]无锁同步栈实现
来源: 互联网 发布时间: 2013-11-19
public class ConcurrentStack<E> {
private AtomicReference<Node<E>> top = new AtomicReference<Node<E>>();
ConcurrentStack(){
}
public void push(E item) {
Node<E> newHead = new Node<E>(item);
Node<E> oldHead = null;
do {
oldHead = top.get();
newHead.next = oldHead;
} while (!top.compareAndSet(oldHead, newHead));
}
public E pop() {
Node<E> newHead = null;
Node<E> oldHead = null;
do {
oldHead = top.get();
if (oldHead == null) { // return null;
continue;
}
newHead = oldHead.next;
} while (oldHead == null || !top.compareAndSet(oldHead, newHead));
return oldHead.item;
}
private static class Node<E> {
public final E item;
public Node<E> next;
public Node(E item) {
this.item = item;
}
}
}
作者：mn11201117 发表于2013-4-10 16:57:27 原文链接
阅读：39 评论：0 查看评论
[2]OpenRisc-22-添加自己的DMA-like ipcore到ORSoC并测试
来源: 互联网 发布时间: 2013-11-19
引言
之前写了一个wishbone接口的slave，work的很好。
但是要想实现一个功能完成的ipcore，必然要有master接口。
这次就写一个ipcore（mycore），既包含slave，又包含master。
一个具有类似DMA功能的ip core。
另：本小节中省略了一些virtualbox下的操作细节，请参考上一篇文章：
http://blog.csdn.net/rill_zhen/article/details/8722664
1，控制流程
1>mycore的linux下的driver写slave
2>slave根据driver发来的指令控制master
3>master进行相应操作，并返回给slave
4>mycore的linux下的driver读slave
2，功能概述
2.1 master写功能
1》driver向slave的num_1寄存器里写入0x11223344
2》driver向slave的write_address寄存器里写入0x00000097.（这是让master 写的地址，其实就是num_1）
3》driver向slave的num_2寄存器里写入0x03000000.（这是让master开始写）
4》打印
5》driver读slave，验证master写入的值是否正确。
2.1.0 模块总连接图
2.1.1 代码修改流程说明：跟单独包含slave的ipcore差不多
1》编写符合wishbone master接口和相应内部逻辑的ip core：mycore
2》d_bus的arbiter增加master接口：master2
3》修改master的仲裁优先级
4》例化本ipcore
5》编写linux下的driver并测试验证
2.1.2 code list：mycore.v,mkg_master.v,mkg_slave.v
1》mycore.v
/* * * mycore.v * * rill create 2013-04-02 * */ `include "orpsoc-defines.v" module mycore ( //===slave interface signals wb_clk, wb_rst, wb_dat_i, wb_adr_i, wb_sel_i, wb_cti_i, wb_bte_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_dat_o, wb_ack_o, wb_err_o, wb_rty_o, //===master interface signals m_adr, m_din, m_dout, m_cyc, m_stb, m_sel, m_we, m_ack, m_err, m_rty, m_cti, m_bte ); //===slave interface input [31:0] wb_adr_i; input wb_stb_i; input wb_cyc_i; input [2:0] wb_cti_i; input [1:0] wb_bte_i; input wb_clk; input wb_rst; input [31:0] wb_dat_i; input [3:0] wb_sel_i; input wb_we_i; output [31:0] wb_dat_o; output wb_ack_o; output wb_err_o; output wb_rty_o; //===master interface input m_ack; input m_err; input m_rty; input [31:0] m_din; output [31:0] m_adr; output [31:0] m_dout; output m_cyc; output m_stb; output [3:0] m_sel; output m_we; output [2:0] m_cti; output [1:0] m_bte; wire [31:0] address; wire [2:0] flag; wire [2:0] test; wire [1:0] done; //===slave external parameters parameter addr_width = 32; parameter mycore_adr = 32'h97; mkg_slave mkg_slave0 ( .address (address), .flag (flag), .test_status (test), .test_done (done), .wb_clk (wb_clk), .wb_rst (wb_rst), .wb_dat_i (wb_dat_i), .wb_adr_i (wb_adr_i), .wb_sel_i (wb_sel_i), .wb_cti_i (wb_cti_i), .wb_bte_i (wb_bte_i), .wb_we_i (wb_we_i), .wb_cyc_i (wb_cyc_i), .wb_stb_i (wb_stb_i), .wb_dat_o (wb_dat_o), .wb_ack_o (wb_ack_o), .wb_err_o (wb_err_o), .wb_rty_o (wb_rty_o) ); mkg_master mkg_master ( .address (address), .flag (flag), .test_status (test), .test_done (done), .wb_clk (wb_clk), .wb_rst (wb_rst), .wb_adr_o (m_adr), .wb_dat_o (m_dout), .wb_sel_o (m_sel), .wb_we_o (m_we), .wb_cyc_o (m_cyc), .wb_stb_o (m_stb), .wb_cti_o (m_cti), .wb_bte_o (m_bte), .wb_dat_i (m_din), .wb_ack_i (m_ack), .wb_err_i (m_err), .wb_rty_i (m_rty) ); endmodule /************** EOF ****************/
2》mkg_master.v
/* * * mkg_master.v * * rill create 2013-04-02 * */ module mkg_master ( address, flag, test_status, test_done, //wishbone interface wb_clk, wb_rst, wb_adr_o, wb_dat_o, wb_sel_o, wb_we_o, wb_cyc_o, wb_stb_o, wb_cti_o, wb_bte_o, wb_dat_i, wb_ack_i, wb_err_i, wb_rty_i ); input [31:0] address; input [2:0] flag; output reg [2:0] test_status; output reg [1:0] test_done; //wishbone interface input wb_clk; input wb_rst; input wb_ack_i; input wb_err_i; input wb_rty_i; input [31:0] wb_dat_i; output reg [31:0] wb_adr_o; output reg [31:0] wb_dat_o; output reg wb_cyc_o; output reg wb_stb_o; output reg [3:0] wb_sel_o; output reg wb_we_o; output reg [2:0] wb_cti_o; output reg [1:0] wb_bte_o; //====master status define parameter m_idle = 3'b000; parameter m_wait_ack_read = 3'b001; parameter m_wait_ack_write = 3'b010; reg [2:0] status = m_idle; reg [31:0] ram_data; always @(posedge wb_clk) begin test_status <= status; end always @(posedge wb_clk) begin if(wb_rst) begin wb_cyc_o <= 1'b0; wb_stb_o <= 1'b0; wb_we_o <= 1'b0; wb_adr_o <= 32'h0; wb_dat_o <= 32'h0; test_done <= 2'b00; status <= m_idle; end else begin case (status) m_idle: begin if(3'd1 == flag)//read begin wb_cyc_o <= 1'b1; wb_stb_o <= 1'b1; wb_adr_o <= address; wb_we_o <= 1'b0; status <= m_wait_ack_read; end else if(3'd2 == flag)//write begin wb_adr_o <= address; wb_dat_o <= 32'h4444_4444; wb_cyc_o <= 1'b1; wb_stb_o <= 1'b1; wb_we_o <= 1'b1; status <= m_wait_ack_write; end else begin wb_cyc_o <= 1'b0; wb_stb_o <= 1'b0; wb_we_o <= 1'b0; wb_adr_o <= 32'h0; wb_dat_o <= 32'h0; status <= m_idle; end end m_wait_ack_read: begin if(1'b1 != wb_ack_i) begin test_done <= 2'b10; status <= m_wait_ack_read; end else begin ram_data <= wb_dat_i; wb_cyc_o <= 1'b0; wb_stb_o <= 1'b0; wb_we_o <= 1'b0; wb_adr_o <= 32'h0; wb_dat_o <= 32'h0; test_done <= 2'b01; status <= m_idle; end end m_wait_ack_write: begin if(1'b1 != wb_ack_i) begin test_done <= 2'b10; status <= m_wait_ack_write; end else begin wb_cyc_o <= 1'b0; wb_stb_o <= 1'b0; wb_we_o <= 1'b0; wb_adr_o <= 32'h0; wb_dat_o <= 32'h0; test_done <= 2'b01; status <= m_idle; end end default: begin status <= m_idle; end endcase end end endmodule /************** EOF ****************/
3》mkg_slave.v
/*
*
* mkg_slave.v
*
* rill create 2013-04-02
*
*/
`include "orpsoc-defines.v"
module mkg_slave
(
address,
flag,
test_status,
test_done,
//===slave interface signals
wb_clk,
wb_rst,
wb_dat_i,
wb_adr_i,
wb_sel_i,
wb_cti_i,
wb_bte_i,
wb_we_i,
wb_cyc_i,
wb_stb_i,
wb_dat_o,
wb_ack_o,
wb_err_o,
wb_rty_o
);
output reg [31:0] address;
output reg [2:0] flag;
input [2:0] test_status;
input [1:0] test_done;
//===slave interface
input [addr_width-1:0] wb_adr_i;
input wb_stb_i;
input wb_cyc_i;
input [2:0] wb_cti_i;
input [1:0] wb_bte_i;
input wb_clk;
input wb_rst;
input [31:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_we_i;
output reg [31:0] wb_dat_o;
output reg wb_ack_o;
output wb_err_o;
output wb_rty_o;
//===slave external parameters
parameter addr_width = 32;
parameter mycore_adr = 8'h97;
//===slave local regs
reg [addr_width-1:0] num_1;//addr index:0x0
reg [addr_width-1:0] num_2;//addr index:0x4
reg [addr_width-1:0] sum;//addr index:0x8
reg [31:0] master_status;//test reg 0xc
reg [31:0] write_address;//0x10
//====slave status define
parameter s_idle = 3'b000;
parameter s_read = 3'b001;
parameter s_write = 3'b010;
reg [2:0] state = s_idle;
reg [1:0] done_flag = 2'b0;
reg [2:0] m_status;
reg [1:0] m_done;
//===mycore process start--->
assign wb_err_o=0;
assign wb_rty_o=0;
//===slave process================
always @(posedge wb_clk)
begin
m_status <= test_status;
m_done <= test_done;
end
always @(posedge wb_clk)
begin
master_status <= {27'b1001_1010_1011_1100_1101_1110_1111_0000,m_status,m_done};
end
always @(*)
begin
sum = num_1 + num_2;
end
always @(posedge wb_clk)
begin
if(wb_rst)
begin
address <= 32'h0;
flag <= 3'b0;
done_flag <= 2'b0;
end
else
begin
if(2'b10 == done_flag)
begin
address <= 32'h0;
flag <= 3'b0;
end
else if(2'b01 == done_flag)
begin
address <= write_address;
flag <= 3'b010;
done_flag <= 2'b10;
end
else
begin
if(3 == num_2)
begin
address <= write_address;
flag <= 3'b010;
done_flag <= 2'b01;
end
else
begin
address <= 32'h0;
flag <= 3'b0;
done_flag <= 2'b00;
end
end
end
end
always @(posedge wb_clk)
begin
if(wb_rst)
begin
state <= s_idle;
end
else
begin
case(state)
s_idle:
begin
wb_dat_o <= 1'b0;
wb_ack_o <= 1'b0;
if(wb_stb_i && wb_cyc_i && wb_we_i)
begin
state <= s_write;
end
else i
[3]nginx的$request_time和$upstream_response_time监控
来源: 互联网 发布时间: 2013-11-19
前言
$request_time&&$upstream_response_time
日志格式
测试
日志
作用
今天老师在trello上给我提了个任务，就是修改nginx的日志格式，对nginx进行监控，因此又接触了两个nginx常用参数，这里记录一下
首先，解释一下这两个参数
- $request_time:nginx处理请求的时间
- $upstream_response_time:php-cgi的响应时间
代码
<?php sleep(5); echo "hello world!<br>"; ?>
作用
我们可以通过代码分析日志，根据$request_time和$upstream_response_time排序获取最耗时的请求，改进代码提高用户体验！
作者：zinss26914 发表于2013-4-10 19:57:15 原文链接
阅读：45 评论：0 查看评论
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